TSMC will start using High-NA EUV in 2030. Intel has already run a million wafers on it

TSMC said this week that it will put High-NA EUV into high-volume manufacturing in 2030, using conventional 6×6-inch photomasks, with a 6×12-inch pilot line in 2031 and 6×12 systems in advanced-node production by 2033. On the same Monday, Intel said it had passed one million 300-mm wafers processed on its High-NA scanners.

Both statements are true and they describe different companies solving the same problem in opposite orders.

High-NA buys you 8 nm single-exposure resolution where today's Low-NA tools give 13 nm. It costs you the field. A 0.55-NA scanner is anamorphic, magnifying 4× in one direction and 8× in the other, so a standard 6×6 mask covers only about 26×16.5 mm on the wafer rather than 26×33 mm. Anything bigger has to be exposed twice and stitched, and on an EXE:5200B stitching probably drops throughput from 175 wafers an hour to 125 (Intel's own figure, and the honest one to quote against itself). That is 29% of the output of a $400 million machine, given up at the door.

So TSMC waited. Which, for a company that ships every large AI die in the world, is not obviously wrong.

TSMC has already said A12 and A13, both due in 2029, stay on conventional EUV. A13 is an optical shrink of A14 that adds about 6% transistor density, so whatever follows it in 2030 likely has to carry a real jump — and that node, whether it ends up called A11 or A10, is the first plausible home for a High-NA layer. Four years out. Two nodes away.

Meanwhile the deferred argument is about glass, not optics.

We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips.

Here is the part nobody has reconciled. TSMC's plan has 6×12 masks in advanced-node production by 2033. ASML's own roadmap, as reported the same day, has every High-NA scanner launched before and after 2033 designed around 6×6 reticles and stitching. One of those two documents is going to move. Changing the mask means changing blanks, deposition, etch, inspection, metrology, cleaning, pellicles, mask writers, handling — and the scanners themselves.

Our read is that TSMC has priced a different bet and is winning it so far. Its answer to the reticle limit has been packaging, not lithography: CoWoS, SoIC, multi-die. And the OIP Forum agenda it opens in Silicon Valley on September 23rd reads accordingly, with Nvidia on multiphysics timing signoff, Arm on cross-die timing analysis, MediaTek on power-network design at the architecture stage, and Alchip on 224G SerDes and photonic co-design. Not one lithography keynote (the packaging track, by contrast, runs to CoWoS, SoIC and co-packaged optics). If your dies are already chiplets, half a field costs you less.

The case against us is Samsung, which plans to bring High-NA into DRAM high-volume manufacturing by 2028 — before TSMC touches it in logic. Memory dies are small and repetitive, which is roughly the shape stitching punishes least, so that may be a cheaper first step than it looks. It still puts TSMC third in a queue it usually leads.

We would expect TSMC to ship no High-NA production wafers before 2030 and A12 to stay on Low-NA as stated. Do you think the mask standard changes by 2033? We would not bet on it, and Intel is the only company acting as though it will.