TSMC will not touch High-NA lithography until 2030. Intel has already run a million wafers on it
TSMC finally put a date on the $400 million scanners, and it is two nodes away, because the argument that decides this is really about the size of a photomask.
Intel has now run more wafers through High-NA lithography than the rest of the industry put together. TSMC has not run one.
Both companies are working on the same problem in opposite orders, and on the same Monday this week they each said so. TSMC will put High-NA EUV into high-volume manufacturing in 2030 on the conventional six-by-six-inch photomasks the industry already uses, with a pilot line for double-width masks the year after and those bigger systems in advanced-node production by 2033 at the earliest. Intel, on the same day, said it had passed one million wafers processed on its own High-NA scanners.
That second number is worth sitting with. In late February 2025 Intel's cumulative count was about thirty thousand. By April 2026 every High-NA scanner ASML had shipped anywhere had processed half a million wafers between them. Intel now beats the whole field by itself.
What High-NA buys, and what it charges
High-NA gets you 8 nm single-exposure resolution where today's Low-NA tools give 13 nm. What it costs you is the field.
A High-NA scanner is anamorphic. It magnifies four times in one direction and eight times in the other, so a standard mask covers about 26 by 16.5 mm on the wafer instead of the full 26 by 33 millimetres.
Anything larger has to be exposed twice and stitched together.
And stitching costs throughput. On ASML's top High-NA tool it falls from 175 wafers an hour to 125, and which is Intel's own figure and the honest one to quote back at Intel (nobody else publishes theirs). Call it 29 percent of the output of a $400 million machine, handed back at the door.
So TSMC waited, which for its customer list is not obviously wrong
TSMC has already said that both of the nodes due in 2029 stay on conventional EUV. The later one is an optical shrink of the node before it and adds roughly 6 percent transistor density, so whatever follows has to carry a real jump. That node, whatever it ends up being called, is the first plausible home for a High-NA layer.
Four years out. Two nodes away.
The argument nobody has reconciled is about glass
ASML's chief executive Christophe Fouquet describes the transition as a progression: "first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity."
Here is the part that does not add up. TSMC's plan has the big masks in advanced-node production by 2033 at the latest. ASML's own roadmap, reported the same day, has every High-NA scanner launched before and after 2033 designed around the small reticles and stitching. One of those two documents has to move.
Changing the mask is not a scanner upgrade. It means changing blanks, deposition, etch, inspection, metrology, cleaning, pellicles, mask writers and handling systems (and the scanners, which is the cheap part of that list).
TSMC bought packaging instead, and is winning that bet so far
Its answer to the reticle limit has never been lithography. CoWoS, SoIC, multi-die.
So read the agenda differently.
Take the OIP Forum it opens in Silicon Valley on 23 September. Nvidia on multiphysics timing signoff. Arm on cross-die timing analysis. MediaTek on power-network design at the architecture stage. Alchip on high-speed SerDes and photonic co-design. Not one lithography keynote (the packaging track, by contrast, runs to CoWoS, SoIC and co-packaged optics). If your dies are already chiplets, half a field costs you less.
The case against us is Samsung, which plans to bring High-NA into DRAM high-volume manufacturing by 2028 and therefore before TSMC touches it in logic at all. Memory dies are small and repetitive, roughly the shape stitching punishes least, so that may be a cheaper first step than it looks from outside. It still puts TSMC third in a queue it usually leads.
We would expect no High-NA production wafers out of TSMC before 2030 and its next high-performance node to stay on Low-NA exactly as stated. Do you think the mask standard changes by 2033? We would not bet on it, and Intel is the only company in the industry acting as though it will.
